The big TEC driver thread!

[dnar]

It lives.

Bipolar PID loop - check
Laser Inhibit - check
Status LED's - check
Current limit - to be completed.

Frank, I had trouble with the NTC op-amp. You had fitted 100R instead of 100K in the negative feedback loop. Now corrected, while it does work, the output is higher than you expected and clips at 4.30V above around 25c. Do you have a board you can check?

Also, for some reason, I have schematic V5 and the part designations do not match the last component overlay you posted. Can you please provide correct matching schematic/overlays please.

[Solarfire]

It lives.

Bipolar PID loop - check
Laser Inhibit - check
Status LED's - check
Current limit - to be completed.

Frank, I had trouble with the NTC op-amp. You had fitted 100R instead of 100K in the negative feedback loop. Now corrected, while it does work, the output is higher than you expected and clips at 4.30V above around 25c. Do you have a board you can check?

Also, for some reason, I have schematic V5 and the part designations do not match the last component overlay you posted. Can you please provide correct matching schematic/overlays please.

Yes I've got a built board here to check. I'll get the correct layout and schematic to you a little later today, kinda all planed out today.

cheers!

[Solarfire]

Frank, I had trouble with the NTC op-amp. You had fitted 100R instead of 100K in the negative feedback loop. Now corrected, while it does work, the output is higher than you expected and clips at 4.30V above around 25c. Do you have a board you can check?

Also, for some reason, I have schematic V5 and the part designations do not match the last component overlay you posted. Can you please provide correct matching schematic/overlays please.

If I understand you correctly with the 100k in place the signal clips @ about >25°C? Is R9 trimmed to aproximatly 930R? It may need to be a little higher, simmulations are not allways 100% but with 930R it was well within the range of the LT1013 and the signal shouldn't clip @ <27°C. Unfortunatly today is a runaround day and I can't check the board today. Could you maybe check the NTC resistance @ 27°C or @ clipping?

Sorry about the 100R, should allways double check!

cheers!

[dnar]

If I understand you correctly with the 100k in place the signal clips @ about >25°C? Is R9 trimmed to aproximatly 930R? It may need to be a little higher, simmulations are not allways 100% but with 930R it was well within the range of the LT1013 and the signal shouldn't clip @ <27°C. Unfortunatly today is a runaround day and I can't check the board today. Could you maybe check the NTC resistance @ 27°C or @ clipping?

Sorry about the 100R, should allways double check!

cheers!

The LT1013 is not rail to rail, so 4.3V is about the limit of it's output. We don't want the non-linearity that occurs her either.

I have made the following tweaks:

R8 changed from 100K to 68K (less gain).
R19 changed from 12K to 13.5K, although this still is not spot on.

With R8 changed and R9 trimmed to provide an ADC input of 4.000V at 27c (90.3k NTC) the minimum is 1.300V at 17c (145k NTC). This is still not good enough as the range 10c - 17c is non-linear. I'll do some more tweaking later.

As it stands, it's working fine 17c - 27c with approx 55 ADC units per C.

[dnar]

I have completed the coding and testing with some good results, despite a few hardware limitations. I have tested with varying thermal loads and the results are good, stable to within 0.02c. I have set the under/over temp LED's to activate +/-0.1c as a result and once locked in, they do not illuminate. The PID tuning values appear to function well regardless of thermal load.

The current bridge decoupling capacitors are not ideally placed electronically, they should be on the traces to the bridge, instead they are wired off as stubs. I had to add 1uF ceramic directly to the bridge supply pins to reduce the rather intense supply noise that effected the analog circuitry through stray board inductance.

I also added 10nF ceramic caps across the 2 negative feedback loops (op-amp o/p to - input) to reduce noise). Several resistors have been changed to dial in the op-amp gains and offsets also.

Another FUBAR on our behalf was the low pass filter on the TEC output. We are stuck with a fixed 8MHz internal clock with the ATtiny and the Fast PWM on timer/counter 0 is set to a clock divisor of 1 and count of 255 with results in the fastest PWM frequency obtainable of 31kHz. While it all works fine, TEC ripple is higher than anticipated. The only solutions are to either use a different MCU with an external crystal @ 20Mhz, or to adjust the LPF components to suit 31kHz. Ideally we should alter the LPF as per the below diagram after further research.


How do you want to proceed Frank? Are you happy for me to document the hardware changes as performed on my sample and provide you with the code so that you may test yourself? I think V2 should proceed with the lessons learned.

Wayne.

[Solarfire]

I have completed the coding and testing with some good results, despite a few hardware limitations. I have tested with varying thermal loads and the results are good, stable to within 0.02c. I have set the under/over temp LED's to activate +/-0.1c as a result and once locked in, they do not illuminate. The PID tuning values appear to function well regardless of thermal load.

Well that sounds good!

The current bridge decoupling capacitors are not ideally placed electronically, they should be on the traces to the bridge, instead they are wired off as stubs. I had to add 1uF ceramic directly to the bridge supply pins to reduce the rather intense supply noise that effected the analog circuitry through stray board inductance.

I also added 10nF ceramic caps across the 2 negative feedback loops (op-amp o/p to - input) to reduce noise). Several resistors have been changed to dial in the op-amp gains and offsets also.

Do you think the 1uF will still be necessary after relocating the decoupling capacitors ?

Another FUBAR on our behalf was the low pass filter on the TEC output. We are stuck with a fixed 8MHz internal clock with the ATtiny and the Fast PWM on timer/counter 0 is set to a clock divisor of 1 and count of 255 with results in the fastest PWM frequency obtainable of 31kHz. While it all works fine, TEC ripple is higher than anticipated. The only solutions are to either use a different MCU with an external crystal @ 20Mhz, or to adjust the LPF components to suit 31kHz. Ideally we should alter the LPF as per the below diagram after further research.

To bad that didn't work out with the 100kHz.

How do you want to proceed Frank? Are you happy for me to document the hardware changes as performed on my sample and provide you with the code so that you may test yourself? I think V2 should proceed with the lessons learned.

Wayne.

Sure go ahead and make the changes. If you can send me the code that would be great to, helps my learning process for getting into this typ of programming.

In the V2 we have the ATmega168, I havn't looked at the datasheet yet, but is it posible to go with the 100kHz on this one, even if an external clk. may be necessary. 31kHz will need a little more on the filtering components side?

cheers!

[dnar]

Do you think the 1uF will still be necessary after relocating the decoupling capacitors ?

Perhaps not.

Sure go ahead and make the changes. If you can send me the code that would be great to, helps my learning process for getting into this typ of programming.

In the V2 we have the ATmega168, I havn't looked at the datasheet yet, but is it posible to go with the 100kHz on this one, even if an external clk. may be necessary. 31kHz will need a little more on the filtering components side?

cheers!

Drop me you current V2 schematic and I'll sus it out.

A few other PCB comments for you: I would like to see more vias dropped to join top/bottom layer ground planes, component pads/holes are much smaller than I like as this makes swapping parts difficult. Minimum clearance from polys to pads is really small also, I had one resistor change result in a short to the ground plane.

There is an exposed net along the edge with the bridge, this shorted when I mounted the board by the bridge. Perhaps the bridge could be moved towards the edge a whisker.

The ISP programming connector is too close to the MCU, the programming plug fouls on the MCU as a result.

I'll put it all together in a report for you soon.

Otherwise, not bad for a first attempt!!! This controller has been very handy during the diode testing of the past 2 weeks!

ATmega168 provides internal RC clocking at 8Mhz also, however may be externally clocked with a 20Mhz XTAL/C. The fastest PWM is then with CTC0/OC0A (8 bit) at 78.125kHz.

[Solarfire]

Drop me you current V2 schematic and I'll sus it out.

On I'ts way shortly...

A few other PCB comments for you: I would like to see more vias dropped to join top/bottom layer ground planes, component pads/holes are much smaller than I like as this makes swapping parts difficult. Minimum clearance from polys to pads is really small also, I had one resistor change result in a short to the ground plane.

Unfortunately Eagle is not that flexible what editing packages on board are concerned. The only way to change the drill diameters of a package is to do it in the library and then reinsert the Schematic symbol so changes will appear on the board. Another possibility is to create a secondary package for a device. Either way it’s a pain in the ass. Usually I work with OrCad, such changes are no problem there.

Adding vias and increasing the poly clearances are no problem to change. The clearances are all at default and passed the DRC.

There is an exposed net along the edge with the bridge, this shorted when I mounted the board by the bridge. Perhaps the bridge could be moved towards the edge a whisker.

Hmm…There shouldn’t be any cooper closer than 20mil from the PCB’s edges?

The ISP programming connector is too close to the MCU, the programming plug fouls on the MCU as a result.

No biggy..

ATmega168 provides internal RC clocking at 8Mhz also, however may be externally clocked with a 20Mhz XTAL/C. The fastest PWM is then with CTC0/OC0A (8 bit) at 78.125kHz.

Do you think it would be worth it to go with the external 20MHz clk. ?

[dnar]

On I'ts way shortly...

Got it, thanks!

Unfortunately Eagle is not that flexible what editing packages on board are concerned. The only way to change the drill diameters of a package is to do it in the library and then reinsert the Schematic symbol so changes will appear on the board. Another possibility is to create a secondary package for a device. Either way it’s a pain in the ass. Usually I work with OrCad, such changes are no problem there.

Eagle is a POS! Hell Orcad? I used to us it back in 1991!!!! It was the fastest tool I have ever used to draw digital schematics... Then I switched to Protel, now I use Altium.

Adding vias and increasing the poly clearances are no problem to change. The clearances are all at default and passed the DRC.

Hmm…There shouldn’t be any cooper closer than 20mil from the PCB’s edges?

Let me check again, pretty sure there is!

Do you think it would be worth it to go with the external 20MHz clk. ?

Yep. At least we can then get closer to 100kHz, and adjust the LPF to suit.

[ogoun]

Any news on version 2?

Cheers,

Pete