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Thread: Poor's man Ilda signal Extender via Ethernet cable

  1. #11
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    Quote Originally Posted by krazer View Post
    There is also the IDN protocol (https://www.ilda.com/resources/Stand...eam_rev001.pdf) but it seems to be very hard to implement (AFAIK the only existing implementations are FPGA based) and not well supported by the laser show software.
    IDN is kind of asymmetric. Usually senders are easier to implement than receivers. But - most of the complexity is due to the signals and timing/quality and not generally protocol related. The only tricky part is the tags and the sample decoding but I'd guess that people who can get hardware like this running will be able to do it.

    Regarding the performance, IDN specifies a minimum of 100kHz for for receivers. The stream can be any resolution or frequency but receivers must have the ability to process minimum requirements.The 100 kHz reflect signal quality of a ISP cable at 5-10 meters.

    The FPGA implementation is essentially the reference platform. This platform was/is to show what is possible. It has a very precise timing and is very low noise. A MCU can absolutely do for standard applications. There is a Raspberry PI implementation... The main thing to keep in mind is memory - but this again is not directly related to IDN. Networking needs memory. Some megabytes. Networkting will be pain to implement otherwise.

  2. #12
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    Thank you guys for your valued suggestions and tricks. Now all clear why i am cuurrently having a distortion issue in the ILDA Image
    as @mixedgas stated in his previously post, i double checked IDN specification. In the IDN Specificition ''For devices sampling the waveforms on the ISP-DB25 connector, the default setting SHALL be a sampling frequency of 100kHz with 100 samples per IDN channel message with the above tags and signal assignments resulting in one message per millisecond of content.''
    For this specification reflesh rate must be at leat 10uS For devices sampling the waveforms. I will sort it out in the very next release and will share here the results.
    Edit:
    I would like to let you know that I just read (ADC Side) and write (DAC Side) X,Y,R,G and B signals. I ignore Intencity and shutter signals. Is that OK ?
    Also i get in progress X / Y signals at 10 bit resolution and R,G,B at 8 bit resolution. Do i need to enhange resolutions ? Actualy When i looked into FB3 they only use 8 bit resolutions for all channels.
    Finaly I am not aware that there is any at least 5 channel DAC working at 100Khz frequency. Any tips i appriciated.
    Best Regards
    Last edited by pyrodigy; 04-26-2019 at 04:02.
    Persistance is the name of the game in this business

  3. #13
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    Quote Originally Posted by pyrodigy View Post
    i double checked IDN specification. In the IDN Specificition ''For devices sampling the waveforms on the ISP-DB25 connector, the default setting SHALL be a sampling frequency of 100kHz with 100 samples per IDN channel message with the above tags and signal assignments resulting in one message per millisecond of content.''

    For this specification reflesh rate must be at leat 10uS For devices sampling the waveforms. I will sort it out in the very next release and will share here the results.
    Edit:
    I would like to let you know that I just read (ADC Side) and write (DAC Side) X,Y,R,G and B signals. I ignore Intencity and shutter signals. Is that OK ?
    Also i get in progress X / Y signals at 10 bit resolution and R,G,B at 8 bit resolution. Do i need to enhange resolutions ? Actualy When i looked into FB3 they only use 8 bit resolutions for all channels.
    Finaly I am not aware that there is any at least 5 channel DAC working at 100Khz frequency. Any tips i appriciated.
    Best Regards
    Regarding IDN:The 100 kHz is a default and a minimum for receivers to be compliant. Remember that this is the sample rate (not the frequency on any wire). Since this is the protocol - this means that you just must be able to receive/handle it (at least). You can output less or more - this is up to you and your hardware... Generally, the 100 k samples per second is high quality (and a good starting point for planning an implementation). Going with 50k will be fine as well - just - keep in mind that you're running into reconstruction (DAC) and anti aliasing (ADC) filter problems the closer your maximum frequency on the wire is to the half of the sample rate (ADC can't be higher because of aliasing -> shannon).

    The FPGA implementation has 16 bit for X/Y/U4 and 12 bit for R/G/B/I/U1/U2/U3. Shutter is transmitted as well.Usually 12 bit converters are pretty affordable. Above that it gets expensive. You could go with all 12 bit. If you take good care about the noise and ringing, you should have great results on X/Y. Alternatively - since there are either 4 or 8 channel DACs you might want to look into two of them. Also - an option in case you have a fast MCU - could be to use a (fast) PWM and L/C or R/C it - same with sigma delta in case it is on the SOC. Reaching the 8 bits or 10 bits (maybe even 12) should be possible.

    Edit: Just a note - for the DAC it is usually good to have a bit of a margin above 100kHz (like 10%). This is not bad because the update rate should not be confused with the settling time. Since the signals are rather slow, settling times slower than 10us are generally OK. The update rate of 100 kHz+10% would be good for synthesizer tuning. Since the output somehow will have to be synchronized to the data stream and therefore to the sender - tuning the output (slower/faster) might be necessary. There are multiple options for this. You could drop/add single samples - or you could tune/tweak your output clock...

    Best regards
    --Dirk
    Last edited by DexLogic; 04-26-2019 at 06:53.

  4. #14
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    @DexLogic
    Thank you for your detailed explain abouth
    sample and frequency rate informations. I will care them every matter in my new design.
    Also FPGA is out of my knowledge, at least i have not able to implement in my projects as yet. I just inspred to start this project as budget friendly and minimum component requirement target.
    Actualy i used MCP series adc and dacs, and 8 bit high performance mcu in this project. In the very next release I am looking forward to use 32 bit arm series mcu and 8 channel 10bit resolution dacs which has lower than 10uS settle time in soon. With them i believe i can able to goal 10us reflesh rate both read from adc and write by dac side.
    Now i m happy with my demo boards, at least it demonstrated that i ve beed good started on this way. i will play with them until i produce better one anyway.
    I will share informations in here.
    Again thank you for the guys you have provided valued information wih me.

    Best regards
    Volkan
    Persistance is the name of the game in this business

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